The present disclosure relates to a semiconductor memory device, and more particularly to an input buffer circuit for receiving an input signal and differentially amplifying and buffering the received input signal.
In general, a semiconductor memory device, such as a dynamic random access memory (DRAM), comprises a memory array including a plurality of memory cells for storing data.
Particularly, in a synchronous DRAM (SDRAM) among various DRAMs, a data read/write operation is carried out synchronously with an external clock signal. For this reason, in the SDRAM, there is a need for an input buffer circuit to generate an internal clock signal which is in synchronization with the external clock signal.
A quadri coupled receiver (QCR) buffer is used in a DRAM as such an input buffer circuit.
Such an input buffer circuit receives an address signal or command signal, as well as a clock signal, converts the received signals into internal signals and then supplies the converted internal signals to respective circuit blocks of the DRAM.
In other words, the input buffer circuit acts to receive and amplify an input of an unstable or weak signal received at the DRAM.
Improved performance of a buffer makes it possible to determine, even when a weak input signal is received, whether the input signal is high or low and shorten the time taken for the input signal to be passed through the buffer.
The amount of current used in operation of the buffer is closely connected with the performance of the buffer.
When the amount of current used is larger, the performance of the buffer becomes better, but the power consumption of the buffer also becomes greater. Conversely, when the amount of current used is smaller, the performance of the buffer is degraded, but the power consumption of the buffer can be reduced.
With the ongoing development of high-speed low-power DRAMs, it has become more difficult and important to properly regulate the amount of current in the buffer. However, in a conventional QCR buffer, there is a shortage of a function of flexibly regulating the amount of current.
FIG. 1 is a circuit diagram of a conventional input buffer circuit. A conventional current regulation function will hereinafter be described with reference to FIG. 1.
The amount of current used in a buffer depends on a sink transistor N5. At a design step, the amount of current is controlled by adjusting the size of the sink transistor. However, at a failure analysis step, it is impossible to adjust the size of the sink transistor. For this reason, a redundant sink transistor N6 is set as an option.
In FIG. 1, N5 is a main sink transistor, and N6 is a redundant sink transistor. If a metal option connected to the drain of the sink transistor N6 is open, the sink transistor N6 is not used. If the metal option is closed, the sink transistor N6 is used to increase the amount of current.
In this manner, in the conventional input buffer circuit, the amount of current is regulated by applying a high or low complementary metal-oxide semiconductor (CMOS) level to the gate of the sink transistor. As a result, there is a problem in that the amount of buffer current is regulated by only one step.